SN65DSI85ZQER Information

SN65DSI85/SN65DSI85-Q1 DSI to FlatLink Bridge

Texas Instruments SN65DSI85/SN65DSI85-Q1 DSI to FlatLink™ Bridge features a dual-channel MIPI D-PHY receiver front-end configuration with four lanes per channel operating at 1Gbps per lane and a maximum input bandwidth of 8Gbps. The bridge decodes MIPI DSI 18bpp RGB666 and 24bpp RGB888 packets. The device also converts the formatted video data-stream to a FlatLink™ compatible LVDS output operating at pixel clocks operating from 25MHz to 154MHz, offering a Dual-Link, Single-Link LVDS, or two Single-Link LVDS interface(s) with four data lanes per link. The SN65DSI85/SN65DSI85-Q1 is well suited for WQXGA (2560 × 1600) at 60 frames per second, as well as 3D Graphics at WUXGA and True HD (1920 × 1080) resolutions at an equivalent 120 fps with up to 24 bits-per-pixel. Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and LVDS interfaces. The SN65DSI85-Q1 devices are AEC-Q100 qualified for automotive applications.

Specifications

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Alternate Names

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